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    VLSI Design with Verilog HDL

    50 Lessons      04:54:26 hrs

    Verilog HDL is an IEEE standard Hardware Description Language used to design and document electronic systems. It is most commonly used in the design, verification, and implementation of digital integrated circuits (IC’s) or digital logic chips.

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    Lesson Plans

    Duration

    Status

    ABL

    Notes

    Excersice


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    • +

      Introduction to VLSI


       

      Integrated Circuit

      09:03

       

      N/A

       

      N/A


       

      Introduction to VLSI

      04:11

       

      N/A

       

      N/A


       

      Applications of VLSI and its Design Styles

      06:33

       

      N/A

       

      N/A


       

      Tools and Languages in VLSI

      03:25

       

      N/A

       

      N/A


    • +

      Hardware Description Languages


       

      Emergence of HDL

      03:55

       

      N/A

       

      N/A


       

      Importance of HDL

      04:22

       

      N/A

       

      N/A


       

      Verilog HDL

      03:41

       

      N/A

       

      N/A


       

      VHDL

      02:59

       

      N/A

       

      N/A


    • +

      Verilog HDL


       

      Typical Design Flow

      04:25

       

      N/A

       

      N/A


       

      Design Methodologies

      04:19

       

      N/A

       

      N/A


       

      Modules and Ports

      07:50

       

      N/A

       

      N/A


       

      Data Types-I

      06:12

       

      N/A

       

      N/A


       

      Data Types-II

      04:09

       

      N/A

       

      N/A


       

      Lexical Conventions-I

      05:26

       

      N/A

       

      N/A


       

      Lexical Conventions-II

      05:51

       

      N/A

       

      N/A


    • +

      Operators


       

      Arithmetic and Bitwise Operators

      07:14

       

      N/A

       

      N/A


       

      Reduction and Shift Operators

      05:15

       

      N/A

       

      N/A


       

      Logical and Relational Operators

      05:42

       

      N/A

       

      N/A


       

      Conditional and Concatenation Operators

      04:28

       

      N/A

       

      N/A


       

      Expressions and Operands

      04:46

       

      N/A

       

      N/A


    • +

      Types of Modeling in Verilog


       

      Gate Level Modeling

      08:06

       

      N/A

       

      N/A


       

      Gate Delays

      05:23

       

      N/A

       

      N/A


       

      Dataflow Modeling

      07:20

       

      N/A

       

      N/A


       

      Behavioral Modeling

      05:40

       

      N/A

       

      N/A


       

      Always Statement

      04:21

       

      N/A

       

      N/A


       

      Procedural Assignments

      05:31

       

      N/A

       

      N/A


       

      Conditional Statements

      07:35

       

      N/A

       

      N/A


       

      Case Statements

      08:30

       

      N/A

       

      N/A


       

      Looping Statements

      07:10

       

      N/A

       

      N/A


       

      Sequential and Parallel Blocks

      07:05

       

      N/A

       

      N/A


       

      Verilog Examples

      09:29

       

      N/A

       

      N/A


       

      Difference between Synchronous and Asynchronous

      01:47

       

      N/A

       

      N/A


    • +

      Structural Modeling and Task Function


       

      Instances and Structural Modeling

      07:58

       

      N/A

       

      N/A


       

      Generate Blocks

      04:32

       

      N/A

       

      N/A


       

      Tasks and Functions

      09:52

       

      N/A

       

      N/A


    • +

      Useful Modeling Techniques in Verilog


       

      Procedural Continuous Assignments

      05:51

       

      N/A

       

      N/A


       

      Overriding Parameters

      05:33

       

      N/A

       

      N/A


       

      Conditional Compilation and Execution

      04:45

       

      N/A

       

      N/A


       

      Time Scales

      03:50

       

      N/A

       

      N/A


       

      System Tasks

      07:51

       

      N/A

       

      N/A


       

      Test Benches

      03:15

       

      N/A

       

      N/A


       

      Timing Delays

      07:11

       

      N/A

       

      N/A


    • +

      Advanced Verilog Topics


       

      Switch Level Modeling

      08:48

       

      N/A

       

      N/A


       

      User Defined Primitives (UDPs)

      05:20

       

      N/A

       

      N/A


       

      Combinational and Sequential UDPs

      10:30

       

      N/A

       

      N/A


       

      Programmable Language Interface

      07:59

       

      N/A

       

      N/A


       

      File Handling

      05:40

       

      N/A

       

      N/A


    • +

      Advanced Verification Techniques


       

      Traditional Verification

      04:19

       

      N/A

       

      N/A


       

      Assertion Checking

      03:41

       

      N/A

       

      N/A


       

      Formal Verification

      05:48

       

      N/A

       

      N/A


    Self Assessment

    Attempts

    Status

    Introduction to VLSI

    0

     


    Hardware Description Languages

    0

     


    Verilog HDL

    0

     


    Operators

    0

     


    Types of Modeling in Verilog

    0

     


    Structural Modeling and Task Function

    0

     


    Useful Modeling Techniques in Verilog

    0

     


    Lesson Plans

    Tips and Tricks

    Glossary

    A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

    ASIC
    An application specific integrated circuit is an integrated circuit or chip which we use for particular application, rather than intended for general purpose use.

    Asynchronous
    Operations in a digital circuit are not executed in time with a clock.